Trading Low Latency System

System Design

Designed to process market data ticks and execute orders with minimal latency. The system handles 10,00k events/second with a p99 latency of 2ms.

Optimization Techniques

1. Lock-Free Data Structures

Used SPSC (Single Producer Single Consumer) queues for generic message passing between threads to avoid kernel-level context switches and mutex contention.

2. Shared Memory IPC

Implemented custom shared memory ring buffers for Inter-Process Communication, significantly faster than TCP loopback.

3. Kernel Bypass (Simulation)

Architected the system to be compatible with Solarflare OpenOnload techniques for future deployment.

Tech Stack